The following logic families are the most frequently used. 
We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. 0000008325 00000 n
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02: WebDiscussion: Digital electronics are built using logic gates. WebBasic Logic Gates. Now that you are able to use the NAND and inverter, use them to construct an AND gate. basic gates; we can create any logic gate or any Boolean expression by combining them. The NAND gate is a universal gate because it can be used to produce the NOT operation, the AND operation, the OR operation, and the NOR operation. 2). 0 0 1 0 0 0 The experiment was also aimed at study of the behavior of the gates such as 74xx series TTL gates by using voltage range of 0 and +5. The computers in the lab have the Metrotrek Waveform Manager Pro software installed that can be used to capture these images; you can save the captured images for later use. 0000004856 00000 n
Electrical and Computer Engineering Department, The objective for this lab will be us designing and verifying a full adder which will be used to create the, 4-bit adder. Looking within the library, we do not have this, option. 0000019247 00000 n
Power dissipation is the supplied power required to operate the desired logic function. 0000002362 00000 n
WebPart 1. 0000019433 00000 n
Throughout this experiment, and throughout the entire course, you may wish to capture images of the oscilloscope display to help you analyze signals and to include in your lab reports. What do you observe? Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates. A logic design that implements a full adder is shown below in Figure 1. WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit. A 2-input AND gate b. Implement Boolean functions using universal gates 6 shows a CMOS transmission gate circuit. To NAND and NOR are called universal gates as using only NAND or only a. An OR Gate works in the opposite way of an AND Gate. 2. Introduce students to the tools, facilities and components needed for the experiments in digital Obbjjeeccttiivveess:: 0000019016 00000 n
Web12. The common CMOS type ICs are in the 4000 series or the pin compatible 74HC00 series. Explain your result. Both input and output signals are not ideal signals, i.e. 5 |H2
E|Loybh%8~E/ PK ! In this first part of the lab, we will be implementing a couple simple logic functions. ECL is used only in systems requiring high-speed operation. TTL and ECL are based upon bipolar transistors. This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. 313 Menu Interface Testing For option selection cursor and option list please, Do not leave children unattended inside the vehicle They could unknowingly ac, 291 Unicode and ASCII code Java uses Unicode a 16 bit encoding scheme, To count the number of cells in column E that contain the text lawn sign in cell, Depreciation expense on the office furniture and fixtures was 7800 for the year, if it is at least 2 standard deviations away from the mean We can therefore, 4 Evaluation of Windows Azure Security The strategy used in this study is based, According to s 760A the main objects of Ch 7 are to promote confident and, Question 20 If a corporation has two classes of shares outstanding rate of, address Address Address But focus on last But focus on last octet octet Last, 2 Describe the Pruitt Prep ferry 3 Who was on the ferry that we have seen in the. Therefore, there can be many ways to define the starting point and the finishing point of the transition process. G^@r#Rd+jJFx
:{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. It was however, noticed that there is a Procedure: Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. 2.0V to 5.0V = Logic 1 and lights the H indicator. These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. For example, the starting and the finishing points are normally chosen at half of the voltage swing of the input and output signals (see Fig. 
3) Then reconstruct the circuit above using only NOR gates. 210 0 obj
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For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. Then move the probe to the output of one of the five parallel inverters, measure the delay again. 0000004299 00000 n
A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. gate separately as universal gates. 2) Complete the Truth table (Table 5-3) and measure the voltages of VA, VB, VC, and VY for each input/output. 7. The, design is symmetric in that the order of the three inputs does not actually matter. 2-input OR gate c. 2-input NAND gate d. 2-input NOR gate e. 2-input XOR gate f. 2-input XNOR gate g. Inverter gate 1. 0000005574 00000 n
There are two functions required to observe and F1 is in the 0000001028 00000 n
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Question 3: What values are you adding? 0000001205 00000 n
End of preview. We see some defects as the logic is settling, like tiny spikes, but it eventually settles to the same value as your behavioral simulation. 0T\N-U9xgsb&. Observe the output on a scope. Introduce students to the tools, facilities and components needed for the experiments in digital 0000000016 00000 n
IC digital logic families. As those To study the truth tables of various basic logic gates using Logisim 2. 0000001394 00000 n
The OpenLab is an open-source, digital platform designed to support teaching and learning at City Tech (New York City College of Technology), and to promote student and faculty engagement in the intellectual and social life of the college community. A Truth Table defines how a combination of gates will react to all possible input combinations. It is made up of a p-type MOS transistor and a n-type MOS transistor. NOR Gate 7 VIII. NAND Gate 8 IX. Note: results may vary The total power dissipation of the whole system, therefore, can be very high. k-70o89*)`Q*`a^0aL -
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The simulation will test the 8 possible combinations for x, y and c_in. A complex electronic system may have many thousands of gates. logical Boolean expression if appropriately designed. 1 shows the circuit symbol, Boolean function, and truth table of AND, OR, inverter, NAND, NOR, and exclusive-OR, respectively. HV]oH}tff`(qhmG5TU+`5j~/={oX|
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HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" The students must save the screenshots each circuit to create a power of CSIS Logic. However, this is not a required step for this lab. MOS and CMOS, are based on field effect transistors. Before we could continue to part 2, we created an IP package that. This laboratory report was done mainly for the study of the logic gates. 0000001719 00000 n
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Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the It has already been discussed above that the NAND (AND + NOT) operation can be replaced by the OR logic on inverted inputs. 0000007220 00000 n
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startxref
Combinational logic requires the use of two or more gates to form a useful, complex function. WebThe most efficient way to quickly reach the fault location is to exploit the low logic level dominance in AND gate and high logic level dominance in OR gate. To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. Lab Report: Digital Logic Figure 9 Results Discussion and Conclusions The results show that the Arithmetic Logic Unit behaved as expected. Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. A Truth Table defines how a gate will react to all possible input combinations. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. endstream
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As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript. A Logic Probe is a piece of test equipment which displays the logic level at a point in the circuit. Then, we captured, the simulation waveforms for the report. 0000001427 00000 n
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We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. 0000008325 00000 n
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02: WebDiscussion: Digital electronics are built using logic gates. WebBasic Logic Gates. Now that you are able to use the NAND and inverter, use them to construct an AND gate. basic gates; we can create any logic gate or any Boolean expression by combining them. The NAND gate is a universal gate because it can be used to produce the NOT operation, the AND operation, the OR operation, and the NOR operation. 2). 0 0 1 0 0 0 The experiment was also aimed at study of the behavior of the gates such as 74xx series TTL gates by using voltage range of 0 and +5. The computers in the lab have the Metrotrek Waveform Manager Pro software installed that can be used to capture these images; you can save the captured images for later use. 0000004856 00000 n
Electrical and Computer Engineering Department, The objective for this lab will be us designing and verifying a full adder which will be used to create the, 4-bit adder. Looking within the library, we do not have this, option. 0000019247 00000 n
Power dissipation is the supplied power required to operate the desired logic function. 0000002362 00000 n
WebPart 1. 0000019433 00000 n
Throughout this experiment, and throughout the entire course, you may wish to capture images of the oscilloscope display to help you analyze signals and to include in your lab reports. What do you observe? Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates. A logic design that implements a full adder is shown below in Figure 1. WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit. A 2-input AND gate b. Implement Boolean functions using universal gates 6 shows a CMOS transmission gate circuit. To NAND and NOR are called universal gates as using only NAND or only a. An OR Gate works in the opposite way of an AND Gate. 2. Introduce students to the tools, facilities and components needed for the experiments in digital Obbjjeeccttiivveess:: 0000019016 00000 n
Web12. The common CMOS type ICs are in the 4000 series or the pin compatible 74HC00 series. Explain your result. Both input and output signals are not ideal signals, i.e. 5 |H2
E|Loybh%8~E/ PK ! In this first part of the lab, we will be implementing a couple simple logic functions. ECL is used only in systems requiring high-speed operation. TTL and ECL are based upon bipolar transistors. This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. 313 Menu Interface Testing For option selection cursor and option list please, Do not leave children unattended inside the vehicle They could unknowingly ac, 291 Unicode and ASCII code Java uses Unicode a 16 bit encoding scheme, To count the number of cells in column E that contain the text lawn sign in cell, Depreciation expense on the office furniture and fixtures was 7800 for the year, if it is at least 2 standard deviations away from the mean We can therefore, 4 Evaluation of Windows Azure Security The strategy used in this study is based, According to s 760A the main objects of Ch 7 are to promote confident and, Question 20 If a corporation has two classes of shares outstanding rate of, address Address Address But focus on last But focus on last octet octet Last, 2 Describe the Pruitt Prep ferry 3 Who was on the ferry that we have seen in the. Therefore, there can be many ways to define the starting point and the finishing point of the transition process. G^@r#Rd+jJFx
:{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. It was however, noticed that there is a Procedure: Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. 2.0V to 5.0V = Logic 1 and lights the H indicator. These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. For example, the starting and the finishing points are normally chosen at half of the voltage swing of the input and output signals (see Fig.
3) Then reconstruct the circuit above using only NOR gates. 210 0 obj
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For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. Then move the probe to the output of one of the five parallel inverters, measure the delay again. 0000004299 00000 n
A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. gate separately as universal gates. 2) Complete the Truth table (Table 5-3) and measure the voltages of VA, VB, VC, and VY for each input/output. 7. The, design is symmetric in that the order of the three inputs does not actually matter. 2-input OR gate c. 2-input NAND gate d. 2-input NOR gate e. 2-input XOR gate f. 2-input XNOR gate g. Inverter gate 1. 0000005574 00000 n
There are two functions required to observe and F1 is in the 0000001028 00000 n
0000010276 00000 n
Question 3: What values are you adding? 0000001205 00000 n
End of preview. We see some defects as the logic is settling, like tiny spikes, but it eventually settles to the same value as your behavioral simulation. 0T\N-U9xgsb&. Observe the output on a scope. Introduce students to the tools, facilities and components needed for the experiments in digital 0000000016 00000 n
IC digital logic families. As those To study the truth tables of various basic logic gates using Logisim 2. 0000001394 00000 n
The OpenLab is an open-source, digital platform designed to support teaching and learning at City Tech (New York City College of Technology), and to promote student and faculty engagement in the intellectual and social life of the college community. A Truth Table defines how a combination of gates will react to all possible input combinations. It is made up of a p-type MOS transistor and a n-type MOS transistor. NOR Gate 7 VIII. NAND Gate 8 IX. Note: results may vary The total power dissipation of the whole system, therefore, can be very high. k-70o89*)`Q*`a^0aL -
2`R,/n?c!Q!OXSw 5hNn 6(4?- A'k
The simulation will test the 8 possible combinations for x, y and c_in. A complex electronic system may have many thousands of gates. logical Boolean expression if appropriately designed. 1 shows the circuit symbol, Boolean function, and truth table of AND, OR, inverter, NAND, NOR, and exclusive-OR, respectively. HV]oH}tff`(qhmG5TU+`5j~/={oX|
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HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" The students must save the screenshots each circuit to create a power of CSIS Logic. However, this is not a required step for this lab. MOS and CMOS, are based on field effect transistors. Before we could continue to part 2, we created an IP package that. This laboratory report was done mainly for the study of the logic gates. 0000001719 00000 n
0000002876 00000 n
Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the It has already been discussed above that the NAND (AND + NOT) operation can be replaced by the OR logic on inverted inputs. 0000007220 00000 n
0000008952 00000 n
startxref
Combinational logic requires the use of two or more gates to form a useful, complex function. WebThe most efficient way to quickly reach the fault location is to exploit the low logic level dominance in AND gate and high logic level dominance in OR gate. To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. Lab Report: Digital Logic Figure 9 Results Discussion and Conclusions The results show that the Arithmetic Logic Unit behaved as expected. Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. A Truth Table defines how a gate will react to all possible input combinations. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. endstream
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As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript. A Logic Probe is a piece of test equipment which displays the logic level at a point in the circuit. Then, we captured, the simulation waveforms for the report. 0000001427 00000 n
LAB TASK#1: Implement the following logic circuit on logic trainer. This will be very, similar to the function we did in lab 1 and lab 2. Basic Gates 3 IV. This is useful as WebTo verify logic truth tables from the voltages measured. WebConsider Discussion Topic #4 before continuing. The 4069 contains 6 of these inverters on one chip. ECE 394 Lab 1: Logic Gates and Logic Families - New Jersey Table 5-4 Truth table and volts measured for input/output for the reconstructed circuit. 4. 7. Use one of the CMOS NAND gates in a 4011 to verify its function and measure its propagation delay for both the rising edge and the falling edge using the same method as in the inverter experiment. Include these measurements within the Discussion Topics of your report. Logic gate or any Boolean expression by combining them required step for lab... Logic function many ways to define the starting point and the finishing point of the lab we. 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